In a multi-level cache system, write requests from a higher cache level that miss have to commit that data to the intended endpoint. These write are typically cached to improve performance. A write miss is treated like a read. Data is allocated in a cache including the write target address. When the allocated data returns it is stored in the cache. The required write then takes place in the cache. This cache line is then marked dirty.
Prior art solutions stalled the CPU and higher cache levels while this write allocate is processed. The entire cache controller stalled until the cache line had been allocated to the cache. This was highly inefficient. Because the CPU request was a write, this should have been processed without such stalls. The prior art did not pipeline write allocates. The cache controller could process only one allocate. The prior art cache controller had to wait until the allocated line was stored before writing data into the allocated cache line. In addition because this prior art committed the write data to the cache after the allocated line was written, all parity and error detection/correction information was lost. This removed soft error protection for this cache line.